1. Technical Field
Example embodiments relate to a nonvolatile memory device and a program verify method thereof and, more particularly, to a nonvolatile memory device and a program verify method thereof, which are capable of improving a distribution of threshold voltages of memory cells.
2. Related Art
A semiconductor memory device is a memory device in which data can be stored and from which stored data can be read. Semiconductor memory devices are chiefly divided into volatile memory devices, whose data stored therein is erased when power is off; and nonvolatile memory devices, whose data stored therein is not erased although power is off. From among the nonvolatile memory devices, flash memory is being widely used in computers, memory cards, etc. because it is capable of electrically erasing bundles of data of memory cells.
Flash memory is divided into NOR-type flash memory and NAND-type flash memory according to a coupling state between memory cells and a bit line. The NOR-type flash memory has two or more cell transistors coupled in parallel to one bit line, stores data using a channel hot electron method, and erases data using a Fowler-Nordheim (F-N) tunneling method. The NAND-type flash memory has two or more cell transistors coupled in series to one bit line and stores or erases data using the F-N tunneling method. In general, the NOR-type flash memory requires higher current consumption, which hinders a high integration of the flash memory. The NOR-type flash memory, however, is superior in terms of having a higher speed. The NAND-type flash memory is able to achieve higher integration because it uses lower cell current than the NOR-type flash memory.
In a program verify method of the nonvolatile memory device, a plurality of program verify operations is consecutively performed by skipping a bit line precharge time during the program verify operation in order to reduce the time taken to perform the program verify operations. If the program verify method is used, however, verify time points are different depending on the program states of memory cells. In this case, there is a problem in that a distribution of the threshold voltages of the memory cells is widened because a margin differs depending on a difference in a time of an evaluation interval when a page buffer detects the potential of a bit line.